? 2004 fairchild semiconductor corporation ds500236 www.fairchildsemi.com january 2000 revised november 2004 74vcx162373 low voltage 16-bit transparent latch 74vcx162373 low voltage 16-bit transparent latch with 3.6v tolerant inputs and outputs and 26 ? series resistors in outputs general description the vcx162373 contains sixteen non-inverting latches with 3-state outputs and is intended for bus oriented applications. the device is byte controlled. the flip-flops appear to be transparent to the data when the latch enable (le) is high. when le is low, the data that meets the setup time is latched. data appears on the bus when the output enable (oe ) is low. when oe is high, the out- puts are in a high impedance state. the vcx162373 is also designed with 26 ? resistors in the outputs. this design reduces line noise in applications such as memory address drivers, clock drivers and bus transceivers/transmitters. the 74vcx162373 is designed for low voltage (1.4v to 3.6v) v cc applications with i/o compatibility up to 3.6v. the 74vcx162373 is fabricated with an advanced cmos technology to achieve high speed operation while maintain- ing low cmos power dissipation. features 1.4v?3.6v v cc supply operation 3.6v tolerant inputs and outputs 26 ? series resistors in outputs t pd (i n to o n ) 3.3 ns max for 3.0v to 3.6v v cc power-off high impedance inputs and outputs support live insertion and withdrawal (note 1) static drive (i oh /i ol ) 12 ma @ 3.0v v cc uses patented noise/emi reduction circuitry latch-up performance exceeds 300 ma esd performance: human body model > 2000v machine model > 200v note 1: to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. ordering code: devices also available in tape and reel. specify by appending suffix letter ? x ? to the ordering code. logic symbol pin descriptions ordering number package package description number 74vcx162373mtd mtd48 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide pin names description oe n output enable input (active low) le n latch enable input i 0 ? i 15 inputs o 0 ? o 15 outputs
www.fairchildsemi.com 2 74vcx162373 connection diagram truth tables h = high voltage level l = low voltage level x = immaterial (high or low, inputs may not float) z = high impedance o 0 = previous o 0 before high-to-low of latch enable functional description the 74vcx162373 contains sixteen edge d-type latches with 3-state outputs. the device is byte controlled with each byte functioning identically, but independent of the other. control pins can be shorted together to obtain full 16-bit operation. the following description applies to each byte. when the latch enable (le n ) input is high, data on the i n enters the latches. in this condition the latches are transparent, i.e., a latch output will change state each time its i input changes. when le n is low, the latches store information that was present on the i inputs a setup time preceding the high-to-low transition on le n . the 3-state outputs are controlled by the output enable (oe n ) input. when oe n is low the standard outputs are in the 2-state mode. when oe n is high, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays. inputs outputs le 1 oe 1 i 0 ?i 7 o 0 ?o 7 xhx z hll l hlhh llxo 0 inputs outputs le 2 oe 2 i 8 ?i 15 o 8 ?o 15 xhx z hll l hlhh llxo 0
3 www.fairchildsemi.com 74vcx162373 absolute maximum ratings (note 2) recommended operating conditions (note 4) note 2: the absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum rat- ings. the ? recommended operating conditions ? table will define the condi- tions for actual device operation. note 3: i o absolute maximum rating must be observed. note 4: floating or unused inputs must be held high or low. dc electrical characteristics supply voltage (v cc ) ? 0.5v to + 4.6v dc input voltage (v i ) ? 0.5v to + 4.6v output voltage (v o ) outputs 3-stated ? 0.5v to + 4.6v outputs active (note 3) ? 0.5v to v cc + 0.5v dc input diode current (i ik ) v i < 0v ? 50 ma dc output diode current (i ok ) v o < 0v ? 50 ma v o > v cc + 50 ma dc output source/sink current (i oh /i ol ) 50 ma dc v cc or gnd current per supply pin (i cc or gnd) 100 ma storage temperature range (t stg ) ? 65 c to + 150 c power supply operating 1.4v to 3.6v input voltage ? 0.3v to + 3.6v output voltage (v o ) output in active states 0v to v cc output in ? off ? state 0.0v to 3.6v output current in i oh /i ol v cc = 3.0v to 3.6v 12 ma v cc = 2.3v to 2.7v 8 ma v cc = 1.65v to 2.3v 3 ma v cc = 1.4v to 1.6v 1 ma free air operating temperature (t a ) ? 40 c to + 85 c minimum input edge rate ( ? t/ ? v) v in = 0.8v to 2.0v, v cc = 3.0v 10 ns/v symbol parameter conditions v cc min max units (v) v ih high level input voltage 2.7 - 3.6 2.0 v 2.3 - 2.7 1.6 1.65 - 2.3 0.65 x v cc 1.4 - 1.6 0.65 x v cc v il low level input voltage 2.7 - 3.6 0.8 v 2.3 - 2.7 0.7 1.65 - 2.3 0.35 x v cc 1.4 - 1.6 0.35 x v cc v oh high level output voltage i oh = ? 100 a 2.7 - 3.6 v cc - 0.2 v i oh = ? 6 ma 2.7 2.2 i oh = ? 8 ma 3.0 2.4 i oh = ? 12 ma 3.0 2.2 i oh = ? 100 a 2.3 - 2.7 v cc - 0.2 i oh = ? 4 ma 2.3 2.0 i oh = ? 6 ma 2.3 1.8 i oh = ? 8 ma 2.3 1.7 i oh = ? 100 a 1.65 - 2.3 v cc - 0.2 i oh = ? 3 ma 1.65 1.25 i oh = ? 100 a 1.4 - 1.6 v cc - 0.2 i oh = ? 1 ma 1.4 1.05
www.fairchildsemi.com 4 74vcx162373 dc electrical characteristics (continued) note 5: outputs disabled or 3-state only. ac electrical characteristics (note 6) symbol parameter conditions v cc min max units (v) v ol low level output voltage i ol = 100 a 2.7 - 3.6 0.2 v i ol = 6 ma 2.7 0.4 i ol = 8 ma 3.0 0.55 i ol = 12 ma 3.0 0.8 i ol = 100 a 2.3 - 2.7 0.2 i ol = 6 ma 2.3 0.4 i ol = 8 ma 2.3 0.6 i ol = 100 a 1.65 - 2.3 0.2 i ol = 3 ma 1.65 0.3 i ol = 100 a 1.4 - 1.6 0.2 i ol = 1 ma 1.4 0.35 i i input leakage current 0 v i 3.6v 1.4 - 3.6 5.0 a i oz 3-state output leakage 0 v o 3.6v, v i = v ih or v il 1.4 - 3.6 10.0 a i off power-off leakage current 0 (v i , v o ) 3.6v 0 10.0 a i cc quiescent supply current v i = v cc or gnd 1.4 - 3.6 20.0 a v cc (v i , v o ) 3.6v (note 5) 1.4 - 3.6 20.0 a ? i cc increase in i cc per input v ih = v cc ? 0.6v 2.7 - 3.6 750 a symbol parameter conditions v cc t a = ? 40 c to + 85 c units figure (v) min max number t phl propagation delay c l = 30 pf, r l = 500 ? 3.3 0.3 0.8 3.6 ns figures 1, 2 t plh le to o n 2.5 0.2 1.0 4.9 1.8 0.15 1.5 9.8 c l = 15 pf, r l = 2k ? 1.5 0.1 1.0 19.6 figures 7, 8 t phl propagation delay c l = 30 pf, r l = 500 ? 3.3 0.3 0.8 3.3 ns figures 1, 2 t plh i n to o n 2.5 0.2 1.0 4.5 1.8 0.15 1.5 9.0 c l = 15 pf, r l = 2k ? 1.5 0.1 1.0 18.0 figures 7, 8 t pzl output enable time c l = 30 pf, r l = 500 ? 3.3 0.3 0.8 3.9 ns figures 1, 3, 4 t pzh 2.5 0.2 1.0 5.4 1.8 0.15 1.5 9.8 c l = 15 pf, r l = 2k ? 1.5 0.1 1.0 19.6 figures 7, 9, 10 t plz output disable time c l = 30 pf, r l = 500 ? 3.3 0.3 0.8 4.0 ns figures 1, 3, 4 t phz 2.5 0.2 1.0 4.4 1.8 0.15 1.5 7.9 c l = 15 pf, r l = 2k ? 1.5 0.1 1.0 15.8 figures 7, 9, 10 t s setup time c l = 30 pf, r l = 500 ? 3.3 0.3 1.5 ns figures 1, 6 2.5 0.2 1.5 1.8 0.15 2.5 c l = 15 pf, r l = 2k ? 1.5 0.1 3.0 figures 6, 7 t h hold time c l = 30 pf, r l = 500 ? 3.3 0.3 1.0 ns figures 1, 6 2.5 0.2 1.0 1.8 0.15 1.0 c l = 15 pf, r l = 2k ? 1.5 0.1 2.0 figures 6, 7
5 www.fairchildsemi.com 74vcx162373 ac electrical characteristics (continued) note 6: for c l = 50 p f, add approximately 300 ps to the ac maximum specification. note 7: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). dynamic switching characteristics capacitance symbol parameter conditions v cc t a = ? 40 c to + 85 c units figure (v) min max number t w pulse width c l = 30 pf, r l = 500 ? 3.3 0.3 1.5 ns figures 1, 5 2.5 0.2 1.5 1.8 0.15 4.0 c l = 15 pf, r l = 2k ? 1.5 0.1 4.0 figures 5, 7 t oshl output to output skew c l = 30 pf, r l = 500 ? 3.3 0.3 0.5 ns t oslh (note 7) 2.5 0.2 0.5 1.8 0.15 0.75 c l = 15 pf, r l = 2k ? 1.5 0.1 1.5 symbol parameter conditions v cc t a = + 25 c units (v) typical v olp quiet output dynamic peak v ol c l = 30 pf, v ih = v cc , v il = 0v 1.8 0.15 v 2.5 0.25 3.3 0.35 v olv quiet output dynamic valley v ol c l = 30 pf, v ih = v cc , v il = 0v 1.8 ? 0.15 v 2.5 ? 0.25 3.3 ? 0.35 v ohv quiet output dynamic valley v oh c l = 30 pf, v ih = v cc , v il = 0v 1.8 1.55 v 2.5 2.05 3.3 2.65 symbol parameter conditions t a = + 25 c units typical c in input capacitance v cc = 1.8v, 2.5v or 3.3v, v i = 0v or v cc 6pf c out output capacitance v i = 0v or v cc , v cc = 1.8v, 2.5v or 3.3v 7 pf c pd power dissipation capacitance v i = 0v or v cc , f = 10 mhz, 20 pf v cc = 1.8v, 2.5v or 3.3v
www.fairchildsemi.com 6 74vcx162373 ac loading and waveforms (v cc 3.3v 0.3v to 1.8v 0.15v) figure 1. ac test circuit figure 2. waveform for inverting and non-inverting functions figure 3. 3-state output high enable and disable times for low voltage logic figure 4. 3-state output low enable and disable times for low voltage logic figure 5. propagation delay, pulse width and t rec waveforms figure 6. setup time, hold time and recovery time for low voltage logic test switch t plh , t phl open t pzl , t plz 6v at v cc = 3.3 0.3v; v cc x 2 at v cc = 2.5 0.2v; 1.8v 0.15v t pzh , t phz gnd symbol v cc 3.3v 0.3v 2.5v 0.2v 1.8v 0.15v v mi 1.5v v cc /2 v cc /2 v mo 1.5v v cc /2 v cc /2 v x v ol + 0.3v v ol + 0.15v v ol + 0.15v v y v oh ? 0.3v v oh ? 0.15v v oh ? 0.15v
7 www.fairchildsemi.com 74vcx162373 ac loading and waveforms (v cc 1.5v 0.1v) figure 7. ac test circuit figure 8. waveform for inverting and non-inverting functions figure 9. 3-state output high enable and disable times for low voltage logic figure 10. 3-state output low enable and disable times for low voltage logic test switch t plh , t phl open t pzl , t plz v cc x 2 at v cc = 1.5v 0.1v t pzh , t phz gnd symbol v cc 1.5v 0.1v v mi v cc /2 v mo v cc /2 v x v ol + 0.1v v y v oh ? 0.1v
www.fairchildsemi.com 8 74vcx162373 low voltage 16-bit transparent latch physical dimensions inches (millimeters) unless otherwise noted 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd48 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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